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2.5 v/3.3 v, 1-bit, 2-port level translator bus switch in sot-66 adg3241 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2006 analog devices, inc. all rights reserved. functional block diagram features 225 ps propagation delay through the switch be a b 04221-001 4.5 switch connection between ports data rate 1.5 gbps 2.5 v/3.3 v supply operation selectable level shifting/translation level translation figure 1. 3.3 v to 2.5 v 3.3 v to 1.8 v 2.5 v to 1.8 v small signal bandwidth 770 mhz tiny 6-lead sc70 package and 6-lead sot-66 package applications 3.3 v to 1.8 v voltage translation 3.3 v to 2.5 v voltage translation 2.5 v to 1.8 v voltage translation bus switching bus isolation hot swap hot plug analog switch applications general description the adg3241 is a 2.5 v or 3.3 v single digital switch. it is designed on a low voltage cmos process that provides low power dissipation yet gives high switching speed and very low on resistance. this allows the input to be connected to the output without additional propagation delay or generating additional ground bounce noise. the switch is enabled by means of the bus enable ( be ) input signal. this digital switch allows a bidirectional signal to be switched when on. in the off condition, signal levels up to the supplies are blocked. this device is ideal for applications requiring level translation. when operated from a 3.3 v supply, level translation from 3.3 v inputs to 2.5 v outputs is allowed. similarly, if the device is operated from a 2.5 v supply and 2.5 v inputs are applied, the device translates the outputs to 1.8 v. in addition to this, a level translating select pin ( sel sel ) is included. when is low, v cc is reduced internally, allowing for level translation between 3.3 v inputs and 1.8 v outputs. this makes the device suited to applications requiring level translation between different supplies, such as converter to dsp/microcontroller interfacing. product highlights 1. 3.3 v or 2.5 v supply operation. 2. extremely low propagation delay through switch. 3. 4.5 switches connect inputs to outputs. 4. level and voltage translation. 5. tiny, sc70 package and sot-66 package.
adg3241 rev. b | page 2 of 16 table of contents features .............................................................................................. 1 applications....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specifications..................................................................................... 3 absolute maximum ratings............................................................ 4 esd caution.................................................................................. 4 pin configuration and function descriptions............................. 5 typical performance characteristics ............................................. 6 terminology .................................................................................... 10 timing measurement information .............................................. 11 bus switch applications ................................................................ 12 mixed voltage operation, level translation.......................... 12 3.3 v to 2.5 v translation ......................................................... 12 2.5 v to 1.8 v translation ......................................................... 12 3.3 v to 1.8 v translation ......................................................... 12 bus isolation................................................................................ 13 hot plug and hot swap isolation............................................. 13 analog switching ....................................................................... 13 high impedance during power-up/power-down................ 13 outline dimensions ....................................................................... 14 ordering guide .......................................................................... 14 revision history 5/06 rev. a to rev. b updated format..................................................................universal changes to table 4............................................................................ 5 changes to ordering guide ......................................................... 14 10/04 rev. 0 to rev. a. changes to features.......................................................................... 1 changes to specifications ................................................................ 2 changes to absolute maximum ratings........................................3 changes to pin configurations .......................................................4 changes to ordering guide .............................................................4 updated outline dimensions....................................................... 11 7/03revision 0: initial version
adg3241 rev. b | page 3 of 16 specifications v cc = 2.3 v to 3.6 v, gnd = 0 v, all specifications t min to t max , unless otherwise noted. 1 table 1. b version parameter symbol conditions min typ 2 max unit dc electrical characteristics input high voltage v inh v cc = 2.7 v to 3.6 v 2.0 v v inh v cc = 2.3 v to 2.7 v 1.7 v input low voltage v inl v cc = 2.7 v to 3.6 v 0.8 v v inl v cc = 2.3 v to 2.7 v 0.7 v input leakage current i i 0.01 1 a off state leakage current i oz 0 a, b v cc 0.01 1 a on state leakage current 0 a, b v cc 0.01 1 a maximum pass voltage v p v a /v b = v cc = sel = 3.3 v, i o = ?5 a 2.2 2.5 2.7 v v a /v b = v cc = sel = 2.5 v, i o = ?5 a 1.5 1.8 2.1 v v a /v b = v cc = 3.3 v, sel = 0 v, i o = ?5 a 1.5 1.8 2.1 v capacitance 3 a port off capacitance c a off f = 1 mhz 3.5 pf b port off capacitance c b off f = 1 mhz 3.5 pf a, b port on capacitance c a , c b on f = 1 mhz 7 pf control input capacitance c in f = 1 mhz 4 pf switching characteristics 3 propagation delay a to b or b to a, t pd 4 t phl , t plh c l = 50 pf, v cc = sel = 3 v 0.225 ns bus enable time be to a or b 5 t pzh , t pzl v cc = 3.0 v to 3.6 v; sel = v cc 1 3.2 4.6 ns bus disable time be to a or b 5 t phz , t plz v cc = 3.0 v to 3.6 v; sel = v cc 1 3 4 ns bus enable time be to a or b 5 t pzh , t pzl v cc = 3.0 v to 3.6 v; sel = 0 v 1 3 4 ns bus disable time be to a or b 5 t phz , t plz v cc = 3.0 v to 3.6 v; sel = 0 v 1 2.5 3.8 ns bus enable time be to a or b 5 t pzh , t pzl v cc = 2.3 v to 2.7 v; sel = v cc 1 3 4 ns bus disable time be to a or b 5 t phz , t plz v cc = 2.3 v to 2.7 v; sel = v cc 1 2.5 3.4 ns maximum data rate v cc = sel = 3.3 v; v a /v b = 2 v 1.5 gbps channel jitter v cc = sel = 3.3 v; v a /v b = 2 v 45 ps p-p digital switch on resistance r on v cc = 3 v, sel = v cc , v a = 0 v, i ba = 8 ma 4.5 8 v cc = 3 v, sel = v cc , v a = 1.7 v, i ba = 8 ma 12 28 v cc = 2.3 v, sel = v cc , v a = 0 v, i ba = 8 ma 5 9 v cc = 2.3 v, sel = v cc , v a = 1 v, i ba = 8 ma 9 18 v cc = 3 v, sel = 0 v, v a = 0 v, i ba = 8 ma 5 8 v cc = 3 v, sel = 0 v, v a = 1 v, i ba = 8 ma 12 power requirements v cc 2.3 3.6 v quiescent power supply current i cc digital inputs = 0 v or v cc ; sel = v cc 0.01 1 a digital inputs = 0 v or v cc ; sel = 0 v 0.1 0.2 ma increase in i cc per input 6 ?i cc v cc = 3.6 v, be = 3.0 v; sel = v cc 0.15 8 a 1 temperature range is as follows: b version: ?40c to +85c. 2 typical values are at 25c, unless otherwise stated. 3 guaranteed by design, not subject to production test. 4 the digital switch contributes no propagation delay other than the rc delay of the typical r on of the switch and the load capacitance when driven by an ideal voltage source. since the time constant is much smaller than the rise/fall times of typical driving signals, it adds very little propag ation delay to the system. propagation delay of the digital switch, when used in a system, is determined by the driving circuit on the driving side of the switch and its in teraction with the load on the driven side. 5 see timing measurement information section. 6 this current applies to the control pin be only. the a and b ports contribute no significant ac or dc currents as they transition.
adg3241 rev. b | page 4 of 16 absolute maximum ratings t a = 25c, unless otherwise noted. table 2. parameter rating stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v cc to gnd ?0.5 v to +4.6 v digital inputs to gnd ?0.5 v to +4.6 v dc input voltage ?0.5 v to +4.6 v dc output current 25 ma per channel operating temperature range only one absolute maximum rating can be applied at any one time. industrial (b version) ?40c to +85c storage temperature range ?65c to +150c junction temperature 150c sc70 package ja thermal impedance 332c/w sot-66 package ja thermal impedance 191c/w (4-layer board) lead temperature, soldering (10 sec) 300c 235c ir reflow, peak temperature (<20 sec) esd caution esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd pr ecautions are recommended to avoid performance degradation or loss of functionality.
adg3241 rev. b | page 5 of 16 pin configuration and fu nction descriptions v cc be sel 04221-002 1 g nd 2 a 3 6 5 b 4 adg3241 top view (not to scale) 1 sel a b gnd be adg3241 top view (not to scale) 2 3 6 5 4 v cc 04221-003 figure 3. 6-lead sot-66 figure 2. 6-lead sc70 table 3. pin function descriptions pin no. sc70 sot-66 mnemonic description be 1 6 bus enable (active low) 2 4 gnd ground reference 3 3 a port a, input or output 4 5 b port b, input or output 5 1 v cc positive power supply voltage sel 6 2 level translation select table 4. truth table be sel function 1 l l a = b, 3.3 v to 1.8 v level shifting l h a = b, 3.3 v to 2.5 v/2.5 v to 1.8 v level shifting h x disconnect 1 sel = 0 v only when v dd = 3.3 v 10%.
adg3241 rev. b | page 6 of 16 typical performance characteristics 0 00 . 5 5 10 15 20 1.5 2.0 1.0 +85c +25c ?40c v cc = 3.3v sel = v cc r on ( ? ) v a /v b (v) 04221-007 0 00.5 5 10 15 20 25 30 35 40 3.0 1.0 r on ( ? ) t a = 25c sel = v cc 1.5 2.0 2.5 3.5 v a /v b (v) v cc = 3v v cc = 3.3v v cc = 3.6v 04221-004 figure 4. on resistance vs. input voltage figure 7. on resistance vs. input voltage for different temperatures 0 5 10 15 00 . 5 1.0 +85c 0 00.5 5 10 15 20 25 30 35 40 3.0 1.0 r on ( ? ) t a = 25c sel = v cc 1.5 2.0 2.5 v a /v b (v) v cc = 2.3v v cc = 2.5v v cc = 2.7v 04221-005 1 . 2 +25c ?40c v cc = 2.5v sel = v cc r on ( ? ) v a /v b (v) 4221-008 0 figure 5. on resistance vs. input voltage figure 8. on resistance vs. input voltage for different temperatures 0 00.5 5 10 15 20 25 30 35 40 3.0 1.0 r on ( ? ) t a = 25c sel = 0v 1.5 2.0 2.5 3.5 v a /v b (v) v cc = 3v v cc = 3.3v v cc = 3.6v 04221-006 0 0.5 1.5 2.5 3.0 2.0 1.0 v out (v) 00.5 3.0 1.0 1.5 2.0 2.5 3.5 v a /v b (v) t a = 25c sel = v cc i o = ?5a v cc = 3.6v v cc = 3.3v v cc = 3v 04221-009 figure 9. pass voltage vs. v cc figure 6. on resistance vs. input voltage
adg3241 rev. b | page 7 of 16 0 0 0.5 1.5 2.5 3.0 2.0 1.0 v out (v) i o (a) 0.02 0.04 0.06 0.08 0.10 t a = 25c v a = 0v be = 0 v cc = sel = 3.3v v cc = sel = 2.5v v cc = 3.3v; sel = 0v 04221-013 0 0.5 1.5 2.5 2.0 1.0 t a = 25c sel = v cc i o = ?5a 00.5 3.0 1.0 1.5 2.0 2.5 v a /v b (v) v cc = 2.3v v cc = 2.5v v cc = 2.7v v out (v) 04221-010 figure 10. pass voltage vs. v cc figure 13. output low characteristic 0 0.5 1.5 2.5 2.0 1.0 t a = 25c sel = 0v i o = ?5a v cc = 3v v cc = 3.3v v cc = 3.6v v out (v) 00.5 3.0 1.0 1.5 2.0 2.5 3.5 v a /v b (v) 04221-011 0 0.5 1.5 2.5 3.0 2.0 1.0 v out (v) i o (a) t a = 25c v a = v cc be = 0 ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 v cc = sel = 3.3v v cc = sel = 2.5v v cc = 3.3v; sel = 0v 0 4221-014 figure 14. output hi gh characteristic figure 11. pass voltage vs. v cc 0 ?0.2 ?0.4 ?0.6 ?0.8 ?1.0 ?1.2 00.5 3.0 1.0 1.5 2.0 2.5 v a /v b (v) q inj (pc) t a = 25c sel = v cc on off c l = 1nf v cc = 3.3v v cc = 2.5v 04221-015 500 enable frequency (mhz) 50 100 150 200 250 300 350 400 450 0 i cc (a) 0 5 10 15 20 25 30 35 40 45 50 t a = 25c v cc = sel = 3.3v v cc = sel = 2.5v v cc = 3.3v; sel = 0v 04221-012 figure 15. charge injection vs. source voltage figure 12. i cc vs. enable frequency
adg3241 rev. b | page 8 of 16 4.0 3.5 3.0 temperature (c) time (ns) 2.5 2.0 1.5 1.0 0.5 0 ?40 ?20 0 20 40 60 80 enable disable v cc = sel = 2.5v 04221-019 2 0 1 ?2 ?1 ?4 ?3 frequency (mhz) attenuation (db) ?6 ?7 ?5 ?8 0.03 0.1 1 10 100 1000 t a = 25c v cc = 3.3v/2.5v sel = v cc v in = 0dbm n/w analyzer: r l = r s = 50 ? 04221-016 figure 19. enable/disable time vs. temperature figure 16. bandwidth vs. frequency data rate (gbps) jitter (ps p-p) 60 70 80 90 100 50 40 30 20 10 0 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 v cc = sel = 3.3v v in = 1.5v p-p 20db attenuation 04221-020 attenu a tion (db) ?90 0 ?100 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 frequency (mhz) 0.1 1 10 100 1000 t a = 25c v cc = 3.3v/2.5v sel = v cc v in = 0dbm n/w analyzer: r l = r s = 50 ? 04221-017 figure 20. jitter vs. data rate; prbs 31 figure 17. off isol ation vs. frequency eye width (%) 60 70 80 85 90 95 100 75 65 55 50 data rate (gbps) 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 v cc = sel = 3.3v v in = 1.5v p-p 20db attenuation % eye width = ((clock period ? jitter p-p)/clock period) 100% 04221-021 4.0 3.5 3.0 temperature (c) time (ns) 2.5 2.0 1.5 1.0 0.5 0 ?40?200 2040 6080 v cc = sel = 3.3v v cc = 3.3v, sel = 0v enable disable enable disable 04221-018 figure 18. enable/disable time vs. temperature figure 21. eye width vs. data rate; prbs 31
adg3241 rev. b | page 9 of 16 50mv/div 200ps/div 20db attenuation t a = 25c v cc = 3.3v sel = 3.3v v in = 1.5v p-p 04221-022 20mv/div 200ps/div 20db attenuation t a = 25c v cc = 2.5v sel = 2.5v v in = 1.5v p-p 0 4221-023 figure 22. eye pattern; 1.5 gbps, v cc = 3.3 v, prbs 31 figure 23. eye pattern; 1.244 gbps, v cc = 2.5 v, prbs 31
adg3241 rev. b | page 10 of 16 terminology v cc positive power supply voltage. gnd ground (0 v) reference. v inh minimum input voltage for logic 1. v inl maximum input voltage for logic 0. i i input leakage current at the control inputs. i oz off state leakage current. it is the maximum leakage current at the switch pin in the off state. i ol on state leakage current. it is the maximum leakage current at the switch pin in the on state. v p maximum pass voltage. the maximum pass voltage relates to the clamped output voltage of an nmos device when the switch input voltage is equal to the supply voltage. r on ohmic resistance offered by a switch in the on state. it is measured at a given voltage by forcing a specified amount of current through the switch. c x off off switch capacitance. c x on on switch capacitance. c in control input capacitance. this consists of be and sel . i cc quiescent power supply current. this current represents the leakage current between the v cc and ground pins. it is measured when all control inputs are at a logic high or low level and the switches are off. i cc extra power supply current component for the be control input when the input is not driven at the supplies. t plh , t phl data propagation delay through the switch in the on state. propagation delay is related to the rc time constant r on c l , where c l is the load capacitance. t pzh , t pzl bus enable times. these are the times taken to cross the v t voltage at the switch output when the switch turns on in response to the control signal, be . t phz , t plz bus disable times. these are the times taken to place the switch in the high impedance off state in response to the control signal. it is measured as the time taken for the output voltage to change by v from the original quiescent level, with reference to the logic level transition at the control input. refer to figure 26 for enable and disable times. max data rate maximum rate at which data can be passed through the switch. channel jitter peak-to-peak value of the sum of the deterministic and random jitter of the switch channel.
adg3241 rev. b | page 11 of 16 timing measurement information for the following load circuit and waveforms, the notation that is used is v in and v out where enable disable 0v 0v 0v v in = 0v v in = v cc v out sw1 @ gnd v out sw1 @ 2v cc t pzl t pzh control input be t phz t plz v t v t v cc v inh v t v cc v l + v v l v h v h ? v 04221-026 v in = v a and v out = v b or v in = v b and v out = v a sw1 gnd dut pulse generator v in r t v cc v out c l r l r l 2 v cc notes 1. pulse generator for all pulses: t r 2.5ns, t f 2.5ns, frequency 10mhz. 2. c l includes board, stray, and load capacitances. 3. r t is the termination resistor, should be equal to z out of the pulse generator. 04221-024 figure 26. enable and disable times table 5. switch position test s1 t plz , t pzl 2 v cc figure 24. load circuit t phz , t pzh gnd 0v v ih v t v h v t v l t plh t plh control input be v out 0 4221-025 figure 25. propagation delay table 6. test conditions symbol v cc = 3.3 v 0.3 v ( sel = v cc ) v cc = 2.5 v 0.2 v ( sel = v cc ) v cc = 3.3 v 0.3 v ( sel = 0 v) nit r l 500 500 500 v 300 150 150 mv c l 50 30 30 pf v t 1.5 0.9 0.9 v
adg3241 rev. b | page 12 of 16 bus switch applications mixed voltage operation, level translation bus switches can provide an ideal solution for interfacing between mixed voltage systems. the adg3241 is suitable for applications where voltage translation from 3.3 v technology to a lower voltage technology is needed. this device can translate from 3.3 v to 1.8 v, from 2.5 v to 1.8 v, or bidirectionally from 3.3 v directly to 2.5 v. figure 27 shows a block diagram of a typical application in which a user needs to interface between a 3.3 v adc and a 2.5 v microprocessor. the microprocessor may not have 3.3 v tolerant inputs, therefore placing the adg3241 between the two devices allows the devices to communicate easily. the bus switch directly connects the two blocks, thus introducing minimal propagation delay, timing skew, or noise. 3.3v adc 2.5 v 3.3 v adg3241 3.3 v 2.5v microprocessor 04221-027 figure 27. level translation between a 3.3 v adc and a 2.5 v microprocessor 3.3 v to 2.5 v translation when v cc is 3.3 v ( sel = 3.3 v) and the input signal range is 0 v to v cc , the maximum output signal will be clamped to within a voltage threshold below the v cc supply. adg3241 2.5v 2.5v 3.3v 2.5v 3.3 v 04221-028 figure 28. 3.3 v to 2.5 v voltage translation, sel = v cc in this case, the output is limited to 2.5 v, as shown in figure 29. this device can be used for translation from 2.5 v to 3.3 v devices and also between two 3.3 v devices. 2 .5 v 0v 3.3v v out switch output switch input v in 3.3v supply sel = 3.3v 04221-029 figure 29. 3.3 v to 2.5 v voltage translation, sel = v cc 2.5 v to 1.8 v translation when v cc is 2.5 v ( sel = 2.5 v) and the input signal range is 0 v to v cc , the maximum output signal is, as before, clamped to within a voltage threshold below the v cc supply. in this case, the output is limited to approximately 1.8 v, as shown in figure 31. adg3241 1.8v 2.5v 2.5 v 04221-030 figure 30. 2.5 v to 1.8 v voltage translation, sel = 2.5 v cc 1.8v 0v 2.5v v out switch output switch input v in 2.5v supply sel = 2.5v 04221-031 figure 31. 2.5 v to 1.8 v voltage translation, sel = v cc 3.3 v to 1.8 v translation the adg3241 offers the option of interfacing between a 3.3 v device and a 1.8 v device. this is possible through the use of the sel pin. the sel pin is an active low control pin. sel activates internal circuitry in the adg3241 that allows voltage translation between 3.3 v devices and 1.8 v devices. adg3241 1.8v 3 .3 v 3.3 v 04221-032 figure 32. 3.3 v to 1.8 v voltage translation, sel = 0 v when v cc is 3.3 v and the input signal range is 0 v to v cc , the maximum output signal is clamped to 1.8 v, as shown in figure 32. to do this, the sel pin must be tied to logic 0. if sel is unused, it should be tied directly to v cc .
adg3241 rev. b | page 13 of 16 card i/o card i/o ram cpu adg3241 adg3241 plug-in card (1) plug-in card (2) bus 04221-035 1.8v 0v 3.3v v out switch output switch input v in 3.3v supply sel = 0v 04221-033 sel figure 33. 3.3 v to 1.8 v voltage translation, = 0 v figure 35. adg3241 in a hot plug application bus isolation a common requirement of bus architectures is low capacitance loading of the bus. such systems require bus bridge devices that extend the number of loads on the bus without exceeding the specifications. because the adg3241 is designed specifically for applications that do not need drive yet require simple logic functions, it solves this requirement. the device isolates access to the bus, thus minimizing capacitance loading. there are many systems, such as docking stations, pci boards for servers, and line cards for telecommunications switches, that require the ability to handle hot swapping. if the bus can be isolated prior to insertion or removal, there is more control over the hot swap event. this isolation can be achieved using bus switches. the bus switches are positioned on the hot swap card between the connector and the devices. during hot swap, the ground pin of the hot swap card must connect to the ground pin of the backplane before any other signal or power pins. bus switch location bus/ backplane load a load c load b load d 04221-034 analog switching bus switches can be used in many analog switching applications, such as video graphics. bus switches can have lower on resistance, smaller on and off channel capacitance, and thus improved frequency performance over their analog counterparts. figure 34. location of bus switched in a bus isolation application hot plug and hot swap isolation the adg3241 is suitable for hot swap and hot plug applications. the output signal of the adg3241 is limited to a voltage that is below the v cc supply, as shown in the bus switch channel itself, consisting solely of an nmos switch, limits the operating voltage (see figure 4 for a typical plot), but in many cases this does not present an issue. figure 29 , figure 31 , and figure 33 . therefore the switch acts like a buffer to take the impact from hot insertion, protecting vital and expensive chipsets from damage. high impedance during power-up/power- down to ensure the high impedance state during power-up or power- down, in hot plug applications, the system cannot be shut down when new hardware is being added. to overcome this, a bus switch can be positioned on the backplane between the bus devices and the hot plug connectors. the bus switch is turned off during hot plug. be should be tied to v cc through a pull-up resistor; the minimum value of the resistor is determined by the current- sinking capability of the driver. figure 35 shows a typical example of this type of application.
adg3241 rev. b | page 14 of 16 outline dimensions compliant to jedec standards mo-203-ab 0.22 0.08 0.30 0.15 1.00 0.90 0.70 seating plane 4 5 6 3 2 1 pin 1 0.65 bsc 1.30 bsc 0.10 max 0.10 coplanarity 0.40 0.10 1.10 0.80 2.20 2.00 1.80 2.40 2.10 1.80 1.35 1.25 1.15 0.46 0.36 0.26 figure 36. 6-lead thin shrink small outline transistor package [sc70] (ks-6) dimensions shown in millimeters seating plane 0.60 0.57 0.53 12 max top view 0.34 max 0.27 nom 0.18 0.17 0.13 bottom view 1.70 1.66 1.50 1.30 1.20 1.10 1.70 1.65 1.50 1 3 5 6 2 4 0.10 nom 0.05 min 0.20 min 0.50 bsc 0.25 max 0.17 min 0.30 0.23 0.10 0.26 0.19 0.11 pin 1 figure 37. 6-lead small outline transistor package [sot-66] (ry-6-1) dimensions shown in millimeters ordering guide temperature range package option model package description branding adg3241bks-reel7 ?40c to +85c 6-lead thin shrink small outline transistor package (sc70) ks-6 ska adg3241bks-500rl7 ?40c to +85c 6-lead thin shrink small outline transistor package (sc70) ks-6 ska ADG3241BKSZ-500RL7 ?40c to +85c 6-lead thin shrink small outline transistor package (sc70) ks-6 s19 1 adg3241bksz-reel7 ?40c to +85c 6-lead thin shrink small outline transistor package (sc70) ks-6 s19 1 adg3241bksz-reel ?40c to +85c 6-lead thin shrink small outline transistor package (sc70) ks-6 s19 1 adg3241bryz-reel7 ?40c to +85c 6-lead small outline transistor package (sot-66) ry-6-1 00 1 1 z = pb-free part.
adg3241 rev. b | page 15 of 16 notes
adg3241 rev. b | page 16 of 16 notes ?2006 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. c04221-0-4/06(b)

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